Modern photolithographic semiconductor fabrication processes produce integrated circuits on a semiconductor wafer by building up patterns in a successive series of layers. A layer is created by exposing light through a photomask to impinge upon a photoresist layer on the wafer. The wafer is then treated with a chemical to remove selected portions of the resist corresponding to the pattern exposed through the photomask. As part of the pattern creation process, the wafer often moves from one photolithography machine to another for the creation of successive layers.
In order to ensure that a working integrated circuit results from the photolithography process various elements within each photolithographic machine, a chuck holding a wafer, and a mask holder holding a mask, must be aligned to ensure each created layer is in the appropriate position in relation to the previous layer. This is overlay, the superposition of a pattern on the surface of a semiconductor device onto a previously etched pattern. Generally, some level of misalignment occurs between the layers during the production process. Overlay control attempts to monitor and correct misalignment between layers on a multi-layer device structure, such as a semiconductor.
Modern overlay control methods model and compensate for inter term misalignment and intra term misalignment. Inter term misalignment is introduced by the photolithographic machine as the wafer is moved from one photolithography machine to another photolithography machine. These photolithographic machine contributions to inter term misalignment include, but are not limited to, variations caused by wafer translation, wafer rotation, and wafer expansion. Intra term misalignment is introduced by the above described contributions of the photolithographic machine and the photomask used to create the layer. These photomask contributions to intra term misalignment include, but are not limited to, mask translation, mask rotation, and mask magnification.
One of the most difficult areas to correct misalignment involves leading lots, the initial group of wafers produced with a photomask and photolithographic machine combination. Processes that attempt to correct misalignment in the leading lot are only able to correct for misalignment caused by the same photolithographic machine, layer, and technology combination used within about the prior 180 days. This is due to the limited amount of historical data that is typically maintained. These processes only correct for misalignment caused by photolithographic machine contributions and not misalignment introduced by the photomask. Consideration of only photolithographic machine contributions to misalignment allows for accurate correction of misalignment in non-leading lots where there is prior experience for the photomask and photolithographic machine combination. Unfortunately, with leading lots there is no prior experience upon which to draw to ensure correct alignment for the leading lot photomask and photolithographic machine combination. Therefore, there is a need for a system and/or method for improved compensation for leading lot overlay that addresses at least some of the problems and disadvantages associated with conventional methods.